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| SSM25T03GH,J N-channel Enhancement-mode Power MOSFET PRODUCT SUMMARY BVDSS R DS(ON) ID DESCRIPTION The SSM25T03 acheives fast switching performance with low gate charge without a complex drive circuit. It is suitable for low voltage applications such as DC/DC converters and general load-switching circuits. The SSM25T03GH is in a TO-252 package, which is widely used for commercial and industrial surface-mount applications. The through-hole version, the SSM250T03GJ in TO-251, is available for vertical mounting, where a small footprint is required on the board, and/or an external heatsink is to be attached. These devices are manufactured with an advanced process, providing improved on-resistance and switching performance. 30V 35m 20A Pb-free; RoHS-compliant TO-251 (IPAK) and TO-252 (DPAK) G D S G D S TO-251 (suffix J) TO-252 (suffix H) ABSOLUTE MAXIMUM RATINGS Symbol VDS VGS ID IDM PD TSTG TJ Parameter Drain-source voltage Gate-source voltage Continuous drain current, TC = 25C TC = 100C Pulsed drain current 1 Value 30 20 20 12 45 20 0.16 -55 to 150 -55 to 150 Units V V A A A W W/C C C Total power dissipation, TC = 25C Linear derating factor Storage temperature range Operating junction temperature range THERMAL CHARACTERISTICS Symbol RJC RJA Parameter Maximum thermal resistance, junction-case Maximum thermal resistance, junction-ambient Value 6 110 Units C/\W C/W Notes: 1.Pulse width must be limited to avoid exceeding the safe operating area. 2.Pulse width <300us, duty cycle <2%. 10/2/2006 Rev.3.1 www.SiliconStandard.com 1 of 6 SSM25T03GH,J ELECTRICAL CHARACTERISTICS Symbol BVDSS Parameter Drain-source breakdown voltage Breakdown voltage temperature coefficient (at Tj = 25C, unless otherwise specified) Test Conditions VGS=0V, ID=250uA Reference to 25C, ID=1mA VGS=10V, ID=12A VGS=4.5V, ID=7A Min. 30 1 Typ. 0.02 13 6 2 4 6 200 10 3 440 105 75 Max. Units 35 55 3 1 25 100 10 705 V V/C m m V S uA uA nA nC nC nC ns ns ns ns pF pF pF BV DSS/Tj RDS(ON) Static drain-source on-resistance VGS(th) gfs IDSS IGSS Qg Qgs Qgd td(on) tr td(off) tf Ciss Coss Crss Gate threshold voltage Forward transconductance VDS=VGS, ID=250uA VDS=10V, ID=12A Drain-source leakage current VDS=30V, VGS=0V VDS=24V ,VGS=0V, Tj =150C VGS=20V ID=12A VDS=24V VGS=4.5V VDS=15V ID=12A RG=3.3 , VGS=10V RD=1.25 VGS=0V VDS=25V f=1.0MHz Gate-source leakage current Total gate charge 2 Gate-source charge Gate-drain ("Miller") charge Turn-on delay time Rise time Turn-off delay time Fall time Input capacitance Output capacitance Reverse transfer capacitance 2 Source-Drain Diode Symbol VSD trr Qrr Parameter Forward voltage 2 Test Conditions IS=12A, VGS=0V IS=12A, VGS=0V, dI/dt=100A/s Min. - Typ. 18 6 Max. Units 1.3 V ns nC Reverse-recovery time 2 Reverse-recovery charge Notes: 1.Pulse width must be limited to avoid exceeding the maximum junction temperature of 150C. 2.Pulse width <300us, duty cycle <2%. 10/2/2006 Rev.3.1 www.SiliconStandard.com 2 of 6 SSM25T03GH,J 50 50 T C =25 C 40 o 10V 7.0V 40 10V T C = 150 C 7.0V ID , Drain Current (A) o ID , Drain Current (A) 30 30 5.0V 20 5.0V 20 4.5V 4.5V 10 10 V G =3.0V 0 0 1 2 3 4 5 0 0 1 2 3 V G =3.0V 4 5 V DS , Drain-to-Source Voltage (V) V DS , Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics 105 1.6 ID=7A 85 1.4 Normalized RDS(ON) T C =25 C o I D = 12 A V G =10V RDS(ON) (m ) 1.2 65 1.0 45 0.8 25 0.6 2 4 6 8 10 -50 0 50 100 150 V GS , Gate-to-Source Voltage (V) T j , Junction Temperature ( o C) Fig 3. On-Resistance vs. Gate Voltage Fig 4. Normalized On-Resistance vs. Junction Temperature 1.8 10 8 Normalized VGS(th) (V) 1.4 6 IS (A) T j =150 o C 4 T j =25 o C 1 0.6 2 0 0.2 0 0.2 0.4 0.6 0.8 1 1.2 -50 0 50 100 150 V SD , Source-to-Drain Voltage (V) T j , Junction Temperature ( o C) Fig 5. Forward Characteristic of Reverse Diode Fig 6. Gate Threshold Voltage vs. Junction Temperature 10/2/2006 Rev.3.1 www.SiliconStandard.com 3 of 6 SSM25T03GH,J f=1.0MHz 14 1000 12 ID=12A C iss V DS =15V V DS =20V V DS =24V C (pF) 100 VGS , Gate to Source Voltage (V) 10 8 C oss C rss 6 4 2 0 0 4 8 12 16 10 1 5 9 13 17 21 25 29 Q G , Total Gate Charge (nC) V DS ,Drain-to-Source Voltage (V) Fig 7. Gate Charge Characteristics Fig 8. Typical Capacitance Characteristics 100 1 Normalized Thermal Response (R thjc) Duty factor=0.5 10 0.2 100us ID (A) 1ms 10ms 100ms DC 0.1 0.1 0.05 PDM 0.02 1 t T Single Pulse T c =25 C Single Pulse 0.1 0.1 1 10 o 0.01 Duty factor = t/T Peak Tj = PDM x Rthjc + T C 0.01 100 0.00001 0.0001 0.001 0.01 0.1 1 V DS ,Drain-to-Source Voltage (V) t , Pulse Width (s) Fig 9. Maximum Safe Operating Area Fig 10. Effective Transient Thermal Impedance 30 V DS =5V 25 VG QG 4.5V QGS QGD ID , Drain Current (A) 20 T j =25 o C T j =150 o C 15 10 5 Charge 0 0 2 4 6 8 Q V GS , Gate-to-Source Voltage (V) Fig 11. Transfer Characteristics Fig 12. Gate Charge Waveform 10/2/2006 Rev.3.1 www.SiliconStandard.com 4 of 6 SSM25T03GH,J PHYSICAL DIMENSIONS: TO-251 (I-PAK) D D1 E2 A SYMBOLS Millimeters MIN NOM MAX c1 A A1 B1 E1 E B2 2.20 0.90 0.50 0.60 0.45 0.45 6.40 5.20 6.80 5.40 1.40 -7.20 1.50 2.30 1.20 0.60 0.72 0.50 0.50 6.60 5.35 7.00 5.60 1.50 2.30 7.50 1.60 2.40 1.50 0.70 0.90 0.60 0.55 6.80 5.50 7.20 5.80 1.60 -7.80 1.80 c c1 D A1 B2 B1 F1 F D1 E E1 E2 e F F1 c 1.All dimensions are in millimeters. 2.Dimensions do not include mold protrusions. e e PHYSICAL DIMENSIONS: TO-252 (D-PAK) E b3 L3 A c2 S Y M B O L TO-252-3L MILLIMETERS MIN. 1.80 0.00 0.40 4.80 0.35 0.40 5.10 6.00 2.30 BSC 7.80 1.00 2.20 0.35 0.50 0.50 0 11.05 2.55 3.05 0.65 2.03 1.20 8 MAX. 2.80 0.13 1.00 5.90 0.65 0.89 6.30 7.00 A A1 D b b3 H L4 c c2 A A SEE VIEW B D E e H e b WITH PLATING c L L1 BASE METAL SECTION A-A L2 L3 L4 GAUGE PLANE SEATING PLANE L VIEW B 10/2/2006 Rev.3.1 www.SiliconStandard.com A1 L2 L1 5 of 6 SSM25T03GH,J PART MARKING PART NUMBER: 25T03GH or 25T03GJ XXXXXX YWWSSS DATE/LOT CODE: (YWWSSS) Y = last digit of the year WW = week SSS = lot code sequence PACKING: Moisture sensitivity level MSL3 TO-252: 3000 pcs in antistatic tape on a reel packed inside a moisture barrier bag (MBB). TO-251: 1000pcs in tubes packed inside a moisture barrier bag (MBB). Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no guarantee or warranty, expressed or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of Silicon Standard Corporation or any third parties. 10/2/2006 Rev.3.1 www.SiliconStandard.com 6 of 6 |
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